1. Field of the Invention
The present invention relates to a thin film semiconductor integrated circuit for driving an active matrix display device in which circuit the power consumption is made smaller than that of conventional circuits by reducing the off-time leak current of P-channel thin film transistors.
The invention also relates to a thin film semiconductor integrated circuit in which the active layer of each constituent thin film transistor (hereinafter called TFT) is made of a silicon semiconductor that has been crystallized by using a catalyst element for accelerating crystallization of amorphous silicon.
2. Description of the Related Art
The active matrix display device is a device in which switching elements are provided for respective pixels and a signal coming through an image signal line is supplied to the pixels through the switching elements. While conventionally TFTs made of an amorphous silicon semiconductor have been used as the switching elements, in recent years TFTs made of a crystalline silicon semiconductor having high operation speed have been developed.
Manufacture of a crystalline silicon semiconductor is associated with the following problems.
A first problem relates to crystallization of silicon. Crystalline silicon is produced by crystallizing amorphous silicon, and two methods for conducting the crystallization are known. In a first method called an optical annealing method, crystallization is instantaneously effected by application of strong light such as laser light. This method has a deficiency of low mass-productivity because a laser oscillator capable of stably producing high-energy light is not available. In a second method called a thermal annealing method or a solid-phase growth method, amorphous silicon is crystallized by solid-phase growth by thermally annealing it usually at 600.degree. C. or a higher temperature. This method are deficient in that the substrate cost is increased because only the quartz substrate can be used when the thermal annealing temperature is 1,000.degree. C., and that the crystallinity of silicon films obtained is not good. Although a low-cost borosilicate glass substrate can be used when the thermal annealing temperature is 600.degree. C., the crystallization takes more than 24 hours.
A second problem is that a TFT made of crystalline silicon has a large leak current when a reverse-bias voltage is applied to the gate electrode. This is believed due to crystal boundaries, and is the most serious problem because the leak current has great influence on the characteristics and power consumption of a crystalline-silicon-based circuit that constitutes an active matrix display device.
In the case of an N-channel TFT, the leak current with negative V.sub.GS is determined by a current flowing through a PN junction between an induced P-type surface layer of a semiconductor thin film and N-type layers of the source and drain regions. Since many traps exist in the semiconductor thin film (particularly in crystal boundaries), this PN junction is incomplete, likely causing a junction leak current. As the gate electrode is negatively biased more deeply, the leak current increases. This is due to a phenomenon that the carrier density of the P-type surface layer formed on the semiconductor thin film is increased to lower the energy barrier height of the PN junction, and resulting electric field concentration increases the junction leak current.
The leak current that occurs in this manner greatly depends on the source-drain voltage. For example, it is known that the leak current sharply increases as the source-drain voltage of a TFT is increased. That is, there may occur a case in which a leak current with a 10-V source-drain voltage is more than 10 times, rather than two times, that with a 5-V source-drain voltage. This nonlinearity also depends on the gate voltage. In general, the difference between leak currents with 5-V and 10-V source-drain voltages increases as the gate electrode is reversely biased more deeply (in an N-channel TFT, as the gate electrode is supplied with a larger negative voltage).
As for the first problem, it is known that the crystallization of amorphous silicon can be accelerated by adding to it a very small amount of nickel (Ni), platinum (Pt), iron (Fe), cobalt (Co), palladium (Pd), or the like (Japanese Unexamined Patent Publication No. Hei. 6-244104). By adding such a catalyst element, crystallization can be effected by thermal annealing typically in 4 hours at 550.degree. C., or in some cases, in a shorter period at a lower temperature. In addition, it has been found that while an amorphous silicon film thinner than 1,000 .ANG. can hardly be crystallized by the conventional thermal annealing method, an amorphous silicon film having a thickness of less than 1,000 .ANG., typically 300 to 800 .ANG., can be crystallized sufficiently by adding a catalyst element to it.
My investigations have revealed that in manufacturing TFTs by using silicon that has been crystallized by adding a catalyst element, it is preferred that the concentration of the catalyst element remaining in silicon be 1.times.10.sup.15 to 5.times.10.sup.19 atoms/cm.sup.3 from the viewpoints of the crystallization step and the characteristics and reliability.
While the first problem has been solved in the above manner, the second problem remains unsolved. Conversely, the resolution of the first problem has caused a new problem of a large variation of the leak current. This is due to the following phenomenon. In the case of a silicon film crystallized by adding a catalyst element, crystal growth proceeds in a needle-like manner (in a grain-like manner in the conventional thermal annealing method) and a resulting crystal has a major-axis diameter of several micrometers or larger (less than 1 .mu.m in the conventional thermal annealing method). Therefore, the TFT characteristics are more influenced by crystal boundaries. FIG. 13 shows a variation of the leak current of a conventional P-channel TFT. As is apparent from FIG. 13, the leak current varies by two orders.
As described above, even where a driving circuit of an active matrix display device is constructed by CMOS (complementary metal oxide semiconductor) TFTs, the power consumption of the entire circuit is large because large leak currents flow through P-channel TFTs even in an off state. Examples of products having an active matrix display device are a notebook-type personal computer and a portable information terminal. At present, the power consumption of the active matrix display device occupies most of the entire power consumption. Therefore, to allow a battery to drive a product for a long time, it is now desired that the power consumption of the active matrix display device be reduced. Further, in view of the trend of saving resources on an earth scale, it is indispensable to reduce the power consumption of the active matrix display device, which is expected to become a next-generation display.